The present invention relates to a device for testing memories which are used to store images, for instance.
In general, a semiconductor memory testing device has such an arrangement as shown in FIG. 1. An address signal is applied to a memory under test 200 from an address terminal 101 of a pattern generator 100 and data created by the pattern generator 100 at that time is provided from its data terminal 102 to the memory 200 and written therein at the specified address. Then, an address signal is applied from the pattern generator 100 to the memory 200 to read out therefrom the stored data. The thus read-out data and data output from the pattern generator 100, that is, expected value data, are compared by a logic comparator 300 to determine whether the memory under test 200 is good or bad.
The pattern generator 100 is made up of an address generator 103, a data generator 104, a data memory 105, a clock control signal generator 106, and a sequence controller 107. The sequence controller 107 controls the address generator 103, the data generator 104, and the clock control signal generator 106. The address generator 103 generates an address signal which is applied to the memory under test 200. The data generator 104 generates, by a logical operation, data for input into the memory 200, that is, write data, and expected value data for input into the logical comparator 300. The data memory 105 also generates data for input into the memory 200 and expected value data for input into the logical comparator 300 which are prestored in the memory 105.
The data generator 104 is used to generate regular data and the data memory 105 to generate irregular, random data. A multiplexer 108 switches between the data generator 104 and the data memory 105. The clock control signal generator 106 generates a clock control signal which is applied to the memory under test 200.
The conventional semiconductor memory testing device shown in FIG. 1 cannot test image memories recently developed. The image memories are each provided with a random access port and a serial access port. The memory is randomly accessed through the random access port. Through the serial access port an initial address is set and is then incremented one by one at high speed in response to a clock, for sequential access to respective memory addresses. A device for testing such a dual port type memory has been proposed in Japanese Patent Application Kokai No. 269076/87, "Semiconductor Memory Testing Device", laid open on Nov. 21, 1987.
There have also been proposed image memories which operate in pixel, plane and block modes. In the case of an image memory for color display, a total of four bits for three color information R, G and B and control information C are employed as minimum pixel information PIX as shown in FIG. 2. The pixel information PIX may sometimes be made eight bits long so as to increase the number of colors used for display. As shown in FIG. 2, the pixel information PIX of an arbitrary address is accessed using an N+1 bits long address signal (A.sub.0 . . . A.sub.N) and sequentially stored in a memory in the depthwise direction of the address. By sequentially or randomly reading out the address in the direction of its depth, the pixel information PIX can be read out or written. This read/write mode is called a pixel mode.
In the plane mode only a single-color information line is accessed by the same number of bits as that of the pixel information PIX.
According to the plane mode, single-color information can be re-written and read out in units of four bits, and a desired area of the display screen can be painted over with the color at high speed. The four-bit signal for effecting the re-write and the read-out at one time will hereinafter be referred to as plane information PLN.
In the block mode a memory space of, for example, a four-by-four bit plane can be read and written at one time. This mode is used for clearing, at high speed, a limited area of the display screen, for example, a multi-window.
Since the dual port type image memory has such various functions as mentioned above, it is difficult for the testing device to create expected value data for testing such functions. It is difficult, in particular, to produce expected value data necessary for reading out, in the plane or block mode, data written in the pixel mode, or for reading out, in the pixel or block mode, data written in the plane mode.
In the testing of a memory capable of inhibiting a write for each bit of data, test data is written into an uninhibited bit but previous data is held in an inhibited bit. The expected value data is therefore determined by previous data, data to be written, and mask data which determines the bit to be inhibited, and consequently, the number of their combinations is large, making it more and more difficult to generate the expected value data.
In the testing of a memory which possesses a logical operation function, it is necessary to determine the expected value data according to data to be applied from a pattern generator, data already written in the memory under test, and the kind of logical operation which is performed in the memory. Also in this instance, the generation of the expected value data is difficult.